Converting a continuous-time analog signal to a discrete-time digital representation typically requires anti-alias filtering, sampling and quantization. An anti-aliasing filter ensures that analog input signal is properly band-limited prior to sampling. A sampler captures samples of the filtered input signal at discrete time intervals, typically T=1/F.sub.s, where F.sub.s is the sampling frequency. The sampling frequency F.sub.s typically is selected as twice the bandwidth of the filtered analog input signal. Finally, a quantizer converts the samples to a discrete set of values. Conventional analog-to-digital (A/D) converters typically perform sampling and quantization, whereas separate discrete components or integrated circuits perform anti-aliasing.
Oversampling A/D converters, in contrast, sample an analog input signal at a rate DF.sub.s that exceeds twice the bandwidth of the analog input signal. An oversampling converter typically includes an anti-alias filter, a sampler and modulator (quantizer) that operate at the elevated rate DF.sub.s, and a digital filter. The digital filter, typically called a decimator, provides low-pass filtering to suppress signals above F.sub.s /2, and sample-rate reduction to lower the sample rate to the desired rate F.sub.s.
As a result of the higher input sampling rate, over-sampling converters have less stringent anti-alias filter requirements than traditional converters. In addition, oversampling converters permit lower quantization noise power, and hence improved signal-to-noise ratio compared to traditional converters.
A/D converters typically operate over a specified maximum and minimum input signal range. The maximum input signal typically is referred to as the converter's full-scale input value. Under ideal conditions, if a full-scale input is applied to the converter, the converter provides a full-scale output. In reality, however, the converter's actual output differs from the ideal result, and the difference between the actual output and the ideal output is the full-scale error. A full-scale accurate converter has zero full-scale error.
A full-scale accurate oversampling converter has significant practical importance in such fields as data acquisition, test and measurement instrumentation, industrial control, etc., because the converter provides a DC-accurate conversion result, exceptional unwanted signal rejection capabilities and simple anti-alias requirements.
Referring to FIG. 1, a common implementation of a delta-sigma oversampling converter is described. Converter 10 includes subtractor circuit 12, integrators 14, and 18, output adder 20, comparator 22, clock generator 24 and digital filter 26.
Based on the state of clock signal CLKA and digital signal Y, subtractor circuit 12 subtracts analog reference signal V.sub.REF from analog input signal V.sub.INPUT. Integrator 14 integrates the resultant error signal E during each cycle of clock signal CLKB and generates output signal IE1. Integrator 16 integrates IE1 during each cycle of clock signal CLKC and generates output signal IE2. Integrator 18 integrates IE2 during each cycle of clock signal CLKD and generates output signal IE3. Output adder 20 produces the algebraic sum of output signals IE1, IE2 and IE3 to create the third-order integrated and feed-forward compensated error signal IE.
Comparator 22 compares error signal IE with an internal reference (not shown) and generates digital output signal Y for every cycle of clock signal CLKE. Digital output Y only has two possible states, and thus can be represented in binary form by a single bit.
Clock generator 24 generates clock signals CLKA, CLKB, CLKC, CLKD and CLKE from external control signal CLK, with appropriate relative phase relations for specific implementations of the modulator blocks.
Digital stream Y contains a digital representation of the ratio R between input signal V.sub.INPUT and reference signal V.sub.REF. Output Y may be extracted and further transformed through digital processing in decimation filter 26. Output D of digital filter 26 is the conversion result.
The full scale output of converter 10 equals the converter's output D.sub.FSI when full-scale signal V.sub.FSI is applied at the converter's input V.sub.INPUT. Under ideal conditions, the ratio of the full-scale input signal V.sub.FSI to V.sub.REF is defined as: ##EQU1## Generally, k is a non-zero proportionality constant, whose value depends upon the convertor's operating range.
As a result of component tolerances and operating condition variations, however, the converter's actual output does not equal D.sub.FSI when V.sub.FSI is applied to the converter's input. Instead, the actual output of the converter equals D.sub.FSI when input signal V.sub.FSA is applied to the converter's input. The ratio between V.sub.FSA and reference signal V.sub.REF is given by: ##EQU2##
The relative full-scale error is defined as: ##EQU3## Under ideal conditions, R.sub.FS =k, and E.sub.FS= 0.
Prior art oversampling A/D converters have used digital calibration to compensate for full-scale error. The AD7714 oversampling A/D converter, for example, manufactured by Analog Devices Inc., Norwood, Mass., implements such an approach. In particular, the AD7714 performs a dedicated full-scale self-calibration conversion during which an internally-generated signal V.sub.FSI is applied to the converter input. Ideally, the converter output is D.sub.D.sub.FSI. The actual output D.sub.FSA is compared to the desired output D.sub.FSI, and a digital computer determines the error E.sub.FS and an appropriate correction factor K.sub.c. Subsequently, the digital computer applies K.sub.c to all converter results D.
The approach used in the AD7714 requires complex circuits that increase converter's size, power consumption and internally-generated noise. Further, a change in environmental conditions invalidates the previously calculated correction coefficient K.sub.c, and requires a new full-scale calibration cycle. Because digital calibration cycles decrease converter throughput, frequent digital calibration results in a reduced equivalent conversion rate.
The full-scale accuracy of converter 10 primarily depends on the accuracy of input subtractor circuit 12. In typical circuit implementations, subtractor circuit 12 and integrator 14 are combined in a single switched-capacitor circuit, and the accuracy of the subtraction function depends on a ratio of two input sampling capacitors. Prior art circuits have attempted to control this critical ratio using well-known integrated circuit layout techniques. Although these layout techniques eliminate the disadvantages related to digital calibration, circuit layout approaches have not achieved the desired level of accuracy.
It therefore would be desirable to provide a delta-sigma analog-to-digital converter that has reduced full-scale error without requiring digital calibration.
It also would be desirable to provide a delta-sigma analog-to-digital converter that has reduced full-scale error without depending on critical capacitor ratios.